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92811 sy 20110606-s00002 no.a1963-1/30 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 LV4904v overview the LV4904v is a 2-channel class-d amplifier ic that supports digital input. with this single chip and with a minimal number of external components, it is possible to effectively implement class-d amplifiers. the LV4904v incorporates a soft mute function and a gain controller without pop noise, and can be used as a master volume control of the set. its function settings can be established through an i 2 c bus interface, but it is also possibl e to establish these settings simply by pin settings without using the i 2 c bus. the LV4904v is ideally suited as the power amplifiers in mini components, flat-panel tvs, game machines, electronic mu sical instruments and other such products. features ? i 2 s input, 2-channel class-d power amplifier ? on-chip variable over-sampler ? gain controller (+12db to -81db, in 1.5 db increments) ? soft mute function ? controllable via i 2 c bus or pin settings ? under voltage protection circuit, overcurrent protec tion circuit, thermal protection circuit integrated functions ? input pcm (fs): 32 khz/44.1 khz/48 khz/88.1 khz/96 khz/176.2 khz/192 khz ? master clock input: 256 fs/384 fs/512 fs/768 fs (when fs=32/44.1/48 khz) ? input format: i 2 s/24 bits left justified msb-first / 24 bits right justified lsb-first / 16/18/20/24 bits right justified msb-first ? output (thd + n=10%) : 10w 2 channels (pvd = 15v, rl = 8 ? ), 15w 2 channels (pvd = 18v, rl = 8 ? ) ? efficiency : 85% (pvd = 15v, rl = 8 ? , fin = 1 khz, po = 10w) ? thd + n : 0.1% or less (pvd = 15v, rl = 8 ? , fin = 1 khz, po = 1w, filter: aes17) ? power supply voltages : pvd = 8 to 20v, vdd = 3.3v orderin g number: ena1963 monolithic ic digital input class-d power amplifier
LV4904v no.a1963-2/25 specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit power cell power supply pvd externally applied power supply -0.3 to 24 v logic power supply v dd externally applied power supply -0.3 to 4.0 v maximum junction temperature tj max 125 c operating temperature topr -30 to +70 c storage temperature tstg -50 to +150 c recommended operating range at ta = 25 c parameter symbol conditions ratings unit min typ max power cell power supply pvd externally applied power supply 8 13 20 v logic power supply v dd externally applied power supply 3.0 3.3 3.6 v load r l speaker load 8 - - electrical characteristics parameter symbol conditions ratings unit min typ max digital/ta=25 c, v dd =3.3v, pvd=13v standby current ipd - 1 10 a operating current i o p - 12 30 ma h input voltage v ih his 0.8v dd - 5.5 v l input voltage v il his -0.3 - 0.2v dd v h input current i i h v in =v dd -- 10 a l input current i i l v in =gnd -10 - - a output pin current i o h v out =v dd -0.4v -0.8 - - ma i o l v out =0.4v 1 - - ma power/ta=25 c, v dd =3.3v, pvd=13v, r l =8 , l=22 h(toko:a7040hn-220m), c=33 f, fin=1khz standby current i st pvd, rstb=low -1 10 a mute on current i mute pvd, enable=low - 1 10 ma quiescent current i cco pvd, 50% duty - 16 60 ma power tr. on resistance *1 r ds on i d =1a - 300 - m output power pout1 8 , 15v, thd+n=10%, modulation index 87.5% 9 10 - w pout2 8 , 18v, thd+n=10%, modulation index 87.5% 12 14 - w output noise v n ihf-a - 4 10 mv thd+n thd p o =1w, 1khz, 8 -0.1 0.3% channel separation chsep p o =1w, 1khz, 8 40 60 - db *1 : the maximum power transistor on resistance(r ds on) is 360m (design guarantee value). note : the value of these characteristics were measured in our test environment. the actual value in an end system will vary de pending on the printed circuit board pattern, the components used, and other factors. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV4904v no.a1963-3/25 package dimensions unit : mm (typ) 3285 pin assignment sanyo : ssop44j(275mil) 7.6 15.0 0.65 5.6 (0.68) (1.5) 44 23 1 22 0.22 0.5 0.2 1.7max side view bottom view top view exposed die-pad 23 22 24 21 25 20 26 19 27 18 28 17 29 16 30 15 31 14 32 13 33 12 34 11 35 10 36 9 37 8 38 7 39 6 40 5 41 4 42 3 43 2 44 1 LV4904v v dd top view rstb v dd v ss v ss enable mck bck lrck sdin dform0 dform1 dform2 mckfs srate ptab2 pvd2 out_ch2_p boot_ch2_p v dd a2 out_ch2_n boot_ch2_n pgnd2 pgnd2 pgnd1 pgnd1 out_ch1_p boot_ch1_p v dd a1 out_ch1_n boot_ch1_n ptab1 pvd1 test mode muteb gain5 gain4 gain3 gain2 gain1 gain0 sda scl pd max -- ta 0 1.02 3.0 1.0 --30 90 30 0 120 2.0 60 ambient temperature , ta -- c allowable power dissipation, pd max -- w specified board : 85.0 59.0 1.5mm 3 glass epoxy(2-layer) 1.32 2.40 1.85 the exposed die-pad is not mounted the exposed die-pad is mounted
LV4904v no.a1963-4/25 application circuit + vd r l 23 22 24 21 25 20 26 19 27 18 28 17 29 16 30 15 31 14 32 13 33 12 34 11 35 10 36 9 37 8 38 7 39 6 40 5 41 4 42 3 43 2 44 1 LV4904v v dd rstb v dd v ss v ss enable mck bck lrck sdin dform0 dform1 dform2 mckfs pvd2 out_ch2_p boot_ch2_p v dd a2 out_ch2_n boot_ch2_n pgnd2 pgnd2 pgnd1 pgnd1 out_ch1_p boot_ch1_p v dd a1 out_ch1_n boot_ch1_n ptab1 pvd1 test mode muteb gain5 gain4 gain3 gain2 gain1 gain0 sda scl - dc 8-20v + v dd - dc 3.3v r l ptab2 srate i 2 c bus control signal mute signal reset signal enable signal i 2 s inputs control signal
LV4904v no.a1963-5/25 block diagram 29 28 26 25 30 16 1 12 13 33 32 4 6 3 2 7 8 9 10 11 42 41 40 39 20 19 17 38 37 36 35 rstb v dd v ss v dd v ss serial/parallel converter over_sampler volume_controller noise_shaping 5 bck lrck sdin mck 34 controller i 2 c i/f 43 44 enable dform0 dform1 dform2 mckfs srate gain0 gain1 gain2 gain3 gain4 gain5 muteb mode test sda scl pwm_converter pwm receiver pwm receiver control delay output stage ch1+ output stage ch1- pwm receiver pwm receiver control delay output stage ch2- output stage ch2+ thermal over current sequence pvd1 out_ch1_p boot_ch1_p out_ch1_n boot_ch1_n out_ch2_p boot_ch2_p out_ch2_n boot_ch2_n 24 pgnd1 23 22 21 pgnd1 pgnd2 pgnd2 15 pvd2 regulator (5v) 27 18 v dd a2 v dd a1 31 ptab1 14 ptab2 v ss pgnd1 pgnd2
LV4904v no.a1963-6/25 pin equivalent circuit pin no. pin name i/o description equivalent circuit 1 rstb di reset input (low active) 2 enable di system enable input 3 mck di master clock input 4 bck di 3-wire serial bit clock input 5 lrck di 3-wire serial lr clock input 6 sdin di 3-wire serial data input 7 dform0 di input format setting input 0 8 dform1 di input format setting input 1 9 dform2 di input format setting input 2 10 mckfs di master clock (mck) rate setting pin 11 srate di input data sampling rate setting pin 12 v dd - digital power supply (3.3v) 13 v ss - small-signal ground (gnd) 14 ptab2 - substrate ground 15 pvd2 - power cell power supply 16 out_ch2_p o output pin, channel 2 (rch) + 16 gnd pvd 17 boot_ch2_p i/o bootstrap i/o pin, channel 2 (rch) + 18 v dd a2 o de-coupling capacitor connection pin for internal power supply 19 boot_ch2_n i/o bootstrap i/o pin, channel 2 (rch) - 20 out_ch2_n o output pin, channel 2 negative 20 gnd pvd 21 pgnd2 - channel 2 power ground 22 pgnd2 - channel 2 power ground 23 pgnd1 - channel 1 power ground 24 pgnd1 - channel 1 power ground 25 out_ch1_n o output pin, channel 1 (lch) - 25 gnd pvd 26 boot_ch1_n i/o bootstrap i/o pin, channel 1 (lch) - 27 v dd a1 o de-coupling capacitor connection pin for internal power supply 28 boot_ch1_p i/o bootstrap i/o pin, channel 1 (lch) + continued on next page.
LV4904v no.a1963-7/25 continued from preceding page. pin no. pin name i/o description equivalent circuit 29 out_ch1_p o output pin, channel 1 (lch) + 29 gnd pvd 30 pvd1 - power cell power supply 31 ptab1 - substrate ground 32 v ss - small-signal ground 33 v dd - digital io power supply (3.3v) 34 test di test mode setting pin (fixed at a low level) 35 mode di output mode setting pin 36 muteb di mute setting input (low active) 37 gain5 di gain setting input 5 38 gain4 di gain setting input 4 39 gain3 di gain setting input 3 40 gain2 di gain setting input 2 41 gain1 di gain setting input 1 42 gain0 di gain setting input 0 43 sda dio [i 2 c i/f] data 44 scl di [i 2 c i/f] bit clock 44
LV4904v no.a1963-8/25 1. mode switching (combined i 2 c bus and pin setting mode ? pin setting mode) 1.1 description of modes combined i 2 c bus and pin setting mode in this mode, the function settings can be established according to both the i 2 c bus and pins. with some pin settings, the settings established according to the i 2 c bus registers are enabled; with the other pin settings, the settings established according to the pins are enabled. pin setting mode in this mode, the LV4904v is controlled only by pin settings. this has the advantage of not requiring the i 2 c bus for control purposes, but the parameters that can be set are limited. table 1.1 below lists the differences between the items that can be set through the i 2 c bus and those that can be set using only the pins. table 1.1 differences between combined i 2 c bus and pin setting mode symbol description settings using the i 2 c bus settings using the pin dform input data format 7 formats available 2 formats available mckfs master clock (mck) rate 4 rates available (256fs, 384fs, 512fs, and 768fs) 2 rates available (256fs and 512fs) srate input data sampling rate 32 khz to 192 khz 44.1 khz to 96 khz gain gain controller setting 2-channel independent ly controllable 2-channel common control mute muting 2-channel independently controllable 2-channel common control pstp pwm output stop setting 2-channel independent ly controllable 2-channel common control idpen 50% pulse setting during mute on or off setting enabled on fixed mdidx modulation index setting 87.5% ? 100% switchable 87.5% fixed nsord noise shaping orders fifth order ? seventh order switchable seventh order fixed 1.2 mode setting methods combined i 2 c bus and pin setting mode the combined i 2 c bus and pin setting mode is established when rstb is set from low to high in a state other than scl=sda=low. however, for this to ha ppen, it is necessary that proper clocks have been input from the mck pin. figure1-1 placing the ic in combined i 2 c bus and pin setting mode pin setting mode the pin setting mode is established when rstb is set fro m low to high in the scl=sda=low state. however, for this to happen, it is necessary that proper clocks have been input from the mck pin. figure1-2 placing the ic in pin setting mode scl sda rstb pin setting mode scl sda rstb combined i 2 c bus and pin setting mode
LV4904v no.a1963-9/25 2. description of pin functions 2.1 hardware reset pin (rstb) rstb is a low active hardware reset pin. the LV4904v is initialized by setting this pin to low. when th e pin is set to low, the internal registers are cleared, and the i 2 c bus registers are also reset to the initial values. table 2.1 shows the rstb function settings. table 2.1 rstb pin functions rstb setting l hardware reset (registers cleared) h for normal operation 2.2 system enable pin (enable) enable is the system enable pin of the LV4904v. when this pin is set to low, the output is muted regardless of any other settings (mute, gain), and the pwm output is stop(set to high-impedance). enable must be set to high in order to activate the LV4904v. if the enable function does not need to be set to on or off, the enable pin can be fixed at high. table 2.2 shows the enable function settings. table 2.2 enable pin function settings enable setting l system disabled h system enabled 2.3 master clock input pin (mck) the master clock is input from the mck pin. for details on this pin, refer to ?8.1 input data settings.? 2.4 3-wire serial data input pins (bck, lrck, sdin) bck, lrck and sdin are pins used for 3-wire serial data input. for details on these pins, refer to ?8.1 input data settings.? 2.5 i 2 c bus pins (scl, sda) scl and sda are the pins used for i 2 c bus communication. the i 2 c bus interface of the lv490 4v does not function as the master but operates only as a slave. scl is the i 2 c bus clock pin and operates only as an input pin. this means that the LV4904v never requests wait by pulling the scl line to low. sda is the i 2 c bus data pin, and since it is an n-channel open drain pin, the data line must be pulled up. for details on the i 2 c bus interface, refer to ?5 i 2 c bus specifications.?
LV4904v no.a1963-10/25 2.6 input data format setting pins (dform0, dform1, dform2) the dform0, dform1 and dform2 pins are set to high or low to match the data format that is input. in the combined i 2 c bus and pin setting mode, the data format settings (table 5.1.1) established according to the i 2 c register are valid when dform0, dform1, and dform2 are low. since the initial setting of the i 2 c register is i 2 s, i 2 s is the setting that is established when dform0, dfor m1, and dform2 are low in the initial state after reset release. table 2.6 shows the format settings established according to the dform0, dform1, and dform2 pins. table 2.6 input data format settings dform2 dform1 dform0 setting combined i 2 c bus and pin setting mode pin setting mode l l l i 2 c register setting i 2 s l l h left justified, msb first l h l right justified, lsb first l h h 24-bit, right ju stified, msb first h l l 20-bit, right ju stified, msb first h l h 18-bit, right ju stified, msb first h h l 16-bit, right ju stified, msb first 2.7 master clock setting pin (mckfs) the mckfs pin is set to high or low to match the rate of the master clock that is to be input from the mck pin. in the combined i 2 c bus and pin setting mode, the master clock settings (table 8.1.2) established according to the i 2 c register are valid when mckfs is low. since the initial setting of the i 2 c register is 256fs, 256fs is the setting that is established when mckfs is low in th e initial state after reset release. if the rate of the clock that is input from the mck pin does not match the mckfs pin or the setting established according to the i 2 c register, an abnormal sound is generated or the output is set to off. table 2.7 shows the mckfs function settings. table 2.7 mckfs pin function settings mckfs setting combined i 2 c bus and pin setting mode pin setting mode l i 2 c register setting 256 fs h 512 fs 2.8 sample rate setting pin (srate) the srate pin is set to high or low to match the sample rate of the input data. in the combined i 2 c bus and pin setting mode, the sample rate settings (table 8.1.2) established according to the i 2 c register are valid when srate is low. since the initial setting of the i 2 c register is 44.1 khz/48 khz, 44.1 khz/48 khz is the setting that is established when srate is low in the initial state after reset release. table 2.8 shows the srate function settings. table 2.8 srate pin function settings srate setting combined i 2 c bus and pin setting mode pin setting mode l i 2 c register setting 44.1 khz/48 khz h 88.2 khz/96 khz
LV4904v no.a1963-11/25 2.9 gain setting pins (gain0, gain1, gain2, gain3, gain4, gain5) the gain can be set by setting the gain0 to gain5 pins to high or low. in the combined i 2 c bus and pin setting mode, the gain settings (table 8.2.1) established according to the i 2 c register are valid when all the gain0 to gain5 pins are low. since the initial setting of the i 2 c register is in mute state, mute is the setting that is established when gain0 to gain 5 are low in the initial state after reset release. table 2.9 shows the gain settings established according to the gain0 to gain5 pins. the gain settings established according to the pin 6 bits and the gain se ttings established according to the register 6 bits are identical, so refer to table 8.2.1 for the detailed settings. table 2.9 gain settings gain5 gain4 gain3 gain2 gain1 gain0 gain setting combined i 2 c bus and pin setting mode pin setting mode h h h h h h +12.0db h h h h h l +10.5db h h h h l h +9.0db ? ? ? ? ? ? (settings in increments of 1.5db) h h h l l l +1.5db h h l h h h 0db h h l h h l -1.5db ? ? ? ? ? ? (settings in increments of 1.5db) l l l l h l -79.5db l l l l l h -81.0db l l l l l l i 2 c register settings mute 2.10 mute pin (muteb) muteb is the low active soft mute pin that controls both the left and right channels. in the combined i 2 c bus and pin setting mode, the mute setting (tab le 8.2.2) established according to the i 2 c register is valid when muteb is low. since the initial setting of the i 2 c register is in mute state, mute is the setting that is established when muteb is low in the initial state after reset release. table 2.10 shows the muteb function settings. table 2.10 muteb pin function settings muteb setting combined i 2 c bus and pin setting mode pin setting mode l i 2 c register setting mute on h mute off 2.11 test mode setting pins (test, mode) test and mode are the test pins. test and mode must be low while using the LV4904v. table 2.11 shows the test, mode function settings. table 2.11 test, mode pin settings test, mode setting l setting when using the LV4904v h inhibited
LV4904v no.a1963-12/25 3. start and stop sequences the start and stop sequences given below are recommended in order to reduce pop noise that occurs when lv4909v is turned on or off. 3.1 start sequence figure 3.1 start sequence 3.2 stop sequence figure 3.2 stop sequence pvd v dd enable rstb mck muteb mutebl_reg mutebr_reg >8.0v >3.0v >2ms >50ms pvd and v dd may be started up in any sequence. i 2 s input i 2 c bus pvd v dd enable rstb muteb mutebl_reg mutebr_reg out_1p/1n out2p/2n >1ms >200ms hi-z pvd and v dd may be stopped in any sequence. out1p/1n out2p/2n (after demodulation)
LV4904v no.a1963-13/25 4. protection circuits the LV4904v is provided with under voltage protection circuit, overcurrent protection circuit and thermal protection circuit. 4.1 under voltage protection circuit in order to prevent unstable operation at low voltages, the under voltage protection circuit monitors the pvd pin voltage, and once the attack voltage (pvd=7v typ.) has been exceeded, it turns on the amplifier. furthermore, the recovery voltage (6v typ.) is set so that unstable operatio n is also prevented when the pvd pin voltage has dropped for some reason during operation. since hysteresis of 1v or so is provided between the attack voltage and recovery voltage, unstable operation near the threshold voltage where the under voltage protection circuit is continuously set to on and off is prevented. figure 4.1 shows the operating model of the under voltage protection circuit. figure 4.1 under voltage protection circuit operation the circuit is designed to turn the amplifier off in the same sequence as when mute is set to on so that this can be used as a measure to prevent pop noise when the primary power for pvd has been turned off. our company?s demonstration board is designed so that the above processes are carried out by the charge stored in the power supply capacitor (470 f) that has been added to the primary power supply line. however, bear in mind that, in the actual products into whic h this ic has been incorporat ed, the primary power supply is connected to other blocks as well, so the time constant for the fall may differ. pvd pin voltage internal control signal recovery voltage
LV4904v no.a1963-14/25 4.2 overcurrent protection circuit the overcurrent protection circuit is for protecting the output transistors from overcurrent. when it has detected an overcurrent caused by shorting to power, shorting to ground or load shorting and the current level has reached 6a or so, it turns off the output transistors for approximately 20 sec. about 20 sec after the output transistors have been turned off, normal operation is recovered automatically, and if another overcurrent is detected, it performs the protection operation again. however, this protection operation is a func tion that temporarily prevents an overcurrent trouble state and it does not guarantee that the ics will not be damaged. figures 4.2.1 and 4.2.2 show the operating models of the overcurrent protection circuit. figure 4.2.1 graphical representation of overcurrent protection circuit operation figure 4.2.2 graphical representation of overcurrent protection circuit operation (enlarged) output current self-recovery & normal operation control operation internal control signal idetect hold time output current internal control signal
LV4904v no.a1963-15/25 4.3 thermal protection circuit the thermal protection circuit is designed to safeguard the ics from damage or deterioration when the ics have generated abnormally high levels of heat. when inadequate heat dissipation, a faulty wiring connection or other factor has caused the ic junction temperature (tj) to rise beyond its rating, the thermal protection circuit sets both the high and low sides of the output transistors to off and places th e output in the high-impedance state. when, after shutdown, the junction temperature has dropped, the ic is automatically recovered. the attack and recovery temperatures of the circuit are provided with hysteresis to prevent unstable operation near the threshold temperature where the thermal protection circuit is continuously set to on and off. however, the thermal protection circuit is a function that temporarily prevents abnormal internal heat generation and does not guarantee that the ics will not be damaged. simila rly, the operating temperature of the thermal protection circuit is not a guaranteed value. figure 4.3 is a graphical representation of the thermal protection circuit. figure 4.3 thermal protection circuit operation output current self-recovery & nomal operation control operation internal control signal
LV4904v no.a1963-16/25 5. i 2 c bus specifications 5.1 overview of i 2 c bus interface the LV4904v supports the standard i 2 c bus interface (max. 100 khz). the device id of the LV4904v is 11011000 (read) and 11011001 (write). its i 2 c bus interface does not function as the ma ster but operates only as a slave. 5.2 i 2 c bus transfer rules in the bus-free state where there is no i 2 c transmission or reception, both the scl and sda pins must be high. from the state in which both pins are high, by holding the scl pin state to high and setting the sda to low, communication is started. this is referre d to as the start condition. to end i 2 c transmission or reception, change the sda pin state from low to high with th e scl still high. this is referred to as the stop condition. data transfer is started after the start condition has been transmitted. the data is transferred in 8-bit units from the master to the LV4904v at the slave, and the LV4904v responds every time 8 bits are received by setting the sda pin to low. this is referred to as acknowledge (ack). the master sets the bus free and waits for ack. 5.3 data write to write data in the LV4904v, the device id, write address an d data are sent in this sequence after the start condition has been sent, and lastly the stop condition is sent. the read/write flag bit is added to the 7-bit device id, and the write mode is established according to setting this bit too low. scl sda h h start condition bus free scl sda h h stop condition bus free scl sda ack ack data is transsferred in 8-bit unit. the LV4904v returns ack each time it has received 8-bit data. start 1 0 r/w ack 1 11 0 0 ack ack stop LV4904v LV4904v LV4904v device id=1101100 write address write data
LV4904v no.a1963-17/25 5.4 data read by sending the data read command, the data held in the regist ers of the LV4904v can be read. to read the data, first the address is sent using a dummy write cycle, and then operation is restarted. next, after the device id and read flag has been sent in the read cycle, the LV4904v outputs the data of the address sent in the dummy write cycle to the sda line. the transmission side establishes the i 2 c bus-free state to prepare for data recep tion. after the data has been received, ack is not returned, and the stop condition is sent to end communication. 5.5 internal register initialization the internal registers accessed at address ffh through the i 2 c bus are write-only registers. by writing the value of ffh into these registers, the internal regi sters are reset to the initial values. 6. i 2 c register map register address d7 d6 d5 d4 d3 d2 d1 d0 stat 00h last accessed address (read-only) data 10h 0 mckfs_i 2 c [1:0] srate_i 2 c [1:0] dform [2:0] gainl 20h pstpl mutebl gainl [5:0] gainr 21h pstpr mutebr gainr [5:0] misc 30h reserved nsord mdidx idpen 1 rst ffh softr [7: 0] (for initializing registers) 7. i 2 c command list register address bit signal name pin description initial value data 10h [2:0] dform 3-wire serial pcm input, format setting 000 [4:3] srate_i 2 c 3-wire serial pcm input, sampling rate setting 01 [6:5] mckfs_i 2 c master clock rate setting 00 [7] 0 (fixed) 0 gainl 20h [5:0] gainl channel 1 (l channel), gain setting 00000 [6] mutebl channel 1 (l channel), mute setting 0 [7] pstpl channel 1 (l channel ), output disable setting 0 gainr 21h [5:0] gainr channel 2 (r channel), gain setting 00000 [6] mutebr channel 2 (r channel), mute setting 0 [7] pstpr channel 2 (r channel), output disable setting 0 misc 30h [0] 1 (fixed) 1 [1] idpen pulse operation control when muted 1 [2] mdidx pwm modulation index setting 0 [3] nsord noise shaper order setting 0 start r/w ack ack ack stop LV4904v LV4904v LV4904v start r/w LV4904v device id read address read data dummy write cycle read cycle device id read address read address start 1 0 r/w ack 1 11 0 0 ack ack stop LV4904v LV4904v LV4904v 1 111 1 111 1 111 1 111 write address=0xff write data=0xff
LV4904v no.a1963-18/25 8. description of i 2 c bus registers 8.1 input data settings register address d7 d6 d5 d4 d3 d2 d1 d0 data 10h 0 mckfs_i 2 c [1: 0] srate_i 2 c [1: 0] dform _i 2 c [2: 0] dform_i 2 c is set to match the format of the 3-wire serial input that is to be input. the setting established according to dform_i 2 c is valid only when the dform0, dform1, and dform2 pins are low in the combined i 2 c bus and pin setting mode. with any other pin settings or when the pin setting mode is established, the settings established according to the pins described in section 2.6 are valid, therefore dform_i 2 c setting described here is ignored. table 16.1.1 and figure 16.1.1 to figure 16.1.4 show the formats that are set by dform_i 2 c. table 8.1.1 data format settings (initial setting in bold ) dform_i 2 c data format 000 i 2 s 001 left justified, msb first 010 right justified, lsb first 011 24 bits, right justified, msb first 100 20 bits, right justified, msb first 101 18 bits, right justified, msb first 110 16 bits, right justified, msb first figure 16.1.1 [dform_i 2 c = 0000] bck=64 fs, i 2 s (24 bits) figure 16.1.2 [dform _i 2 c = 0001] bck=64 fs, left justified, msb first (24 bits) figure 16.1.3 [dform _i 2 c = 0010] bck=64 fs, right justified, lsb first (24 bits) figure 8.1.4 [dform_i 2 c = 011/100/101/110] bck=64 fs, 24/20/18/16 bits, right justified, msb first 23 22 21 20 3 2 1 0 23 22 21 20 3 2 1 0 23 22 21 32fs lch 32fs rch 23 22 21 20 3 2 1 0 23 22 21 20 3 2 1 0 23 22 21 32fs lch 32fs rch 20 23 22 21 3 2 1 0 23 22 21 20 3 2 1 0 23 22 21 32fs lch 32fs rch 20 0 1 2 0 1 2 3 0 1 2 32fs lch 32fs rch 3 24/20/18/16 bit 24/20/18/16 bit
LV4904v no.a1963-19/25 master clock rate mckfs_i 2 c and sample rate srate_i 2 c are set in accordance with the master clock and input sample rate. the settings established according to mckfs_i 2 c are valid only when the mckfs pin is set to low in the combined i 2 c bus and pin setting mode. when mckfs is high or when the pin setting mode is established, the settings established according to the pins described in s ection 2.7 are valid, therefore mckfs_i 2 c setting described here is ignored. the settings established according to srate_i 2 c are valid only when the srate pin is low in the combined i 2 c bus and pin setting mode. when srate is high or when the pin setting mode is established, the settings established according to the pins described in section 2.8 are valid, therefore srate_i 2 c setting described here is ignored. if these settings are illegal and they do not match the input signals , an abnormal sound is generated or the output is set to off. noise is generated when switching the settings, so mute the output before changing any settings. table 8.1.2 shows the settings of the master clock that is set by srate and mckfs. table 8.1.2 master clock settings (initial values in bold ) srate_i 2 c sampling rate mckfs_i 2 c setting and mck rate [1] [0] [00] [01] [10] [11] 0 0 32 khz 256 fs 384 fs 512 fs 768 fs 0 1 44.1/48 khz 256 fs 384 fs 512 fs 768 fs 1 0 88.2/96 khz 128 fs 192 fs 256 fs 384 fs 1 1 176.4/192 khz 64 fs 96 fs 128 fs 192 fs 8.2 gain and mute settings register address d7 d6 d5 d4 d3 d2 d1 d0 gainl 20h pstpl mutebl gainl [5:0] gainr 21h pstpr mutebr gainr [5:0] the left-channel volume and right-channel volume are each set with 6 bits and in 64 steps using the gainl and gainr registers, respectively. the volume setting ranges from +12 db to -81 db in 1.5 db increments. the settings established according to gainl and gainr are va lid only when all the gain0 to gain5 pins are low in the combined i 2 c bus and pin setting mode. with any other pin settings or when the pin setting mode is established, the settings established according to the pins described in section 2.9 are valid, therefore gainl and gainr setting described here is ignored. table 8.2.1 shows the volume settings established according to gainl and gainr. table 8.2.1 gain settings (initial value in bold ) no. gainl gainr gain (db) no. gainl gainr gain (db) no. gainl gainr gain (db) 63 111111 +12.0 41 101001 -21.0 19 010011 -54.0 62 111110 +10.5 40 101000 -22.5 18 010010 -55.5 61 111101 +9.0 39 100111 -24.0 17 010001 -57.0 60 111100 +7.5 38 100110 -25.5 16 010000 -58.5 59 111011 +6.0 37 100101 -27.0 15 00 1111 -60.0 58 111010 +4.5 36 100100 -28.5 14 001110 -61.5 57 111001 +3.0 35 100011 -30.0 13 001101 -63.0 56 111000 +1.5 34 100010 -31.5 12 001100 -64.5 55 110111 0.0 33 100001 -33.0 11 001011 -66.0 54 110110 -1.5 32 100000 -34.5 10 001010 -67.5 53 110101 -3.0 31 0 11111 -36.0 9 001001 -69.0 52 110100 -4.5 30 0 11110 -37.5 8 001000 -70.5 51 110011 -6.0 29 011101 -39.0 7 000111 -72.0 50 110010 -7.5 28 011100 -40.5 6 000110 -73.5 49 110001 -9.0 27 011011 -42.0 5 000101 -75.0 48 110000 -10.5 26 011010 -43.5 4 000100 -76.5 47 101111 -12.0 25 01 1001 -45.0 3 000011 -78.0 46 101110 -13.5 24 011000 -46.5 2 000010 -79.5 45 101101 -15.0 23 010111 -48.0 1 000001 -81.0 44 101100 -16.5 22 010110 -49.5 0 000000 mute 43 101011 -18.0 21 010101 -51.0 42 101010 -19.5 20 010100 -52.5
LV4904v no.a1963-20/25 left channel mute is set using mutebl and right chan nel mute is set using mutebr. both mutebl and mutebr are low active. the settings established according to mutebl and mutebr are valid only when the muteb pin is low in the combined i 2 c bus and pin setting mode. with any other pin settings or when the pin setting mode is established, the settings established according to the pins described in section 2.10 are valid, ther efore mutebl and mutebr setting described here is ignored. table 8.2.2 shows the mute settings esta blished according to mutebl and mutebr. table 8.2.2 mute settings (initial value in bold ) mutebl/mutebr setting 0 mute 1 audio output on the left channel pwm output can be stopped by pstpl and the right channel pwm output can be stopped by pstpr. table 8.2.3 shows the pwm output stop settings established according to pstpl and pstpr. table 8.2.3 pwm output stop settings (initial value in bold ) pstpl/pstpr setting 0 normal output operation mode 1 pwm output stopped 8.3 other settings register address d7 d6 d5 d4 d3 d2 d1 d0 pwm1 41h reserved nsord mdidx idpen 1 by setting idpen, the pwm output can be fixed to the 50% dut y cycle pulse or idled during mute or under no-signal conditions. table 8.3.1 shows the idpen function settings. table 8.3.1 idpen function settings (initial value in bold ). idpen setting 0 idle operation mode 1 50% duty pulse the modulation index of the pwm modulator can be switched by setting mdidx. table 8.3.2 shows the mdidx function settings. table 8.3.2 mdidx function settings (initial value in bold ). mdidx setting 0 87.5% 1 100% the noise shaper order can be switched by setting nsord. table 8.3.3 shows the nsord function settings. table 8.3.3 nsord function settings (initial value in bold ) nsord setting 0 seventh order 1 fifth order
LV4904v no.a1963-21/25 8. characteristics data: ta=27 c , fs=48 khz, master clock=256 fs ipd -- v dd 0 0.1 0.02 2.6 3.2 3.0 2.8 3.4 3.6 3.8 10 8 6 4 2121416 10 8 6 4121416 4.0 ipd -- ta 0 0.6 0.1 -40 0 60 100 ist -- pvd 0 0.3 0.4 0.2 0.1 0.5 018 ist -- ta 0 imute -- pvd 0 2 1 10 0 2 1 3 4 5 18 imute -- ta i cco -- pvd 0 20 0 10 20 i cco -- ta 0.04 0.06 0.08 rstb=low v dd =3.3v rstb=low 0.2 0.4 0.8 -20 20 20 40 80 rstb=low 20 0.3 0.4 0.2 0.1 0.5 pvd=15v rstb=low -40 0 60 100 -20 20 20 40 80 r l =8 rstb=high enable=low 20 -40 0 60 100 -20 20 40 80 vd=15v r l =8 rstb=high enable=low 6 -40 0 60 100 -20 20 40 80 10 8 6 41214161820 r l =8 rstb=high enable=high muteb=low 30 30 40 50 vd=15v r l =8 rstb=high enable=high muteb=low ambient temperature, ta - c ambient temperature, ta - c ambient temperature, ta - c ambient temperature, ta - c muting current, imute - ma muting current, imute - ma quiescent current, i cc - ma quiescent current, i cc - ma standby current, ipd - a standby current, ipd - a power supply, v dd - v power cell power supply, pvd - v power cell power supply, pvd - v power cell power supply, pvd - v
LV4904v no.a1963-22/25 iop -- v dd 0 20 5 2.6 3.2 3.0 2.8 3.4 3.6 3.8 10 9121416 4.0 i cc -- ta 0 15 20 -40 0 60 100 v dd a -- pvd v dd a -- ta v no -- pvd 0 10 2 0.1 1 18 v no -- ta ch sep. -- pvd 0 -20 ch sep. -- ta 10 15 pvd=15v rstb=high enable=high mute=low 5 10 -20 20 20 40 80 -40 0 60 100 -20 20 20 40 80 r l =8 rstb=high enable=high muteb=high v o l=+12db ihf-a 20 -40 0 60 100 -20 20 40 80 10 -40 0 60 100 -20 20 40 80 vd=15v r l =8 rstb=high enable=high muteb=low v dd a -v 10 8 6 41214161820 0 2 1 3 4 5 6 r l =8 rstb=high enable=high muteb=low v dd a -v 0 2 1 3 4 5 6 vd=15v r l =8 rstb=high enable=high muteb=low 4 6 8 11 13 15 17 19 vd=15v r l =8 v in =-138dbfs v o l=+12db ihf-a 10 91214161820 11 13 15 17 19 r l =8 f in =1khz vo=0dbm d in audio -40 -60 -80 0 -20 -40 -60 -80 vd=15v r l =8 f in =1khz v o =0dbm aes17 ambient temperature, ta - c power supply, v dd - v ambient temperature, ta - c ambient temperature, ta - c ambient temperature, ta - c quiescent current, i cc - ma noise, v no -- mvrms channel separation, chsep. -- db noise, v no -- mvrms channel separation, chsep. -- db power cell power supply, pvd - v power cell power supply, pvd - v power cell power supply, pvd - v operating current, iop - ma
LV4904v no.a1963-23/25 0 25 5 10 power -- ta 0 15 20 -40 0 60 100 thd+n -- pvd thd+n -- ta thd+n -- frequency 10 15 5 10 -20 20 20 40 80 -40 0 60 100 -20 20 20 40 80 100000 pvd=15v r l =8 f in =1khz thd+n=10% 2ch-drive aes17 0.01 0.1 1 10 100 1000 10000 power -- pvd 10 91214161820 11 13 15 17 19 r l =8 f in =1khz 2ch-drive pcl=0x00 aes17 20 87.5% modulation 100% modulation 87.5% modulation 100% modulation power - w power - w 10 91214161820 11 13 15 17 19 0.01 0.1 1 10 r l =8 f in =1khz po=1w 2ch-drive vol=+12db aes17 ch1 ch2 ch1 ch2 pvd=15v r l =8 po=1w 2ch-drive vol=+12db aes17 0.01 0.1 10 1 pvd=15v r l =8 po=1w 2ch-drive vol=+12db aes17 ch2 ch1 0.001 thd+n -- power 10 0.01 0.1 1 0.01 0.1 10 1 pvd=15v r l =8 2ch-drive v ol=+12db aes17 power - w 0.0001 100hz 1khz 6.67khz 0.001 thd+n -- power 10 0.01 0.1 1 0.01 0.1 10 1 pvd=15v r l =8 2ch-drive v ol=+12db aes17 power - w 0.0001 ch1 ch2 ambient temperature, ta - c ambient temperature, ta - c power supply, v dd - v power cell power supply, pvd - v frequency - hz total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- % total harmonic distortion, thd+n -- %
LV4904v no.a1963-24/25 0 100 20 10 power -- v in 1 10 1 1000 i d -- power pd -- power response -- frequency 40 60 0.01 0.1 10 100 100000 0 0.5 1 2 100 1000 10000 power -- efficiency 2 0610 48 80 efficiency - % power - w 2 0610 48 0 1 2 6 -10 10 0 ch2 ch1 pvd=15v r l =8 f in =1khz 2ch-drive aes17 power - w 100 0.001 0.0001 v in - mffs pvd=15v r l =8 f in =1khz 2ch-drive vol=+12db aes17 i d - a power - w pvd=15v r l =8 f in =1khz 2ch-drive aes17 1.5 power - w pd - w 2 0610 48 pvd=15v r l =8 f in =1khz 2ch-drive aes17 3 4 5 pvd=15v r l =8 po=1w 2ch-drive vol=+12db aes17 -8 -6 -4 -2 2 4 6 8 power -- ta 0 6 10 -40 0 60 100 2 4 -20 20 20 40 80 upper power - w rl=8 rstb=high enable=high muteb=high 8 lower ambient temperature, ta - c frequency - hz response - db
LV4904v ps no.a1963-25/25 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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